1. Field of the Invention
This invention relates to an electronic component carrier and a method of producing the same as well as an electronic device using the same, and more particularly to an electronic component carrier having structural characteristics in the vicinity of a lead frame for mounting an electronic component such as a semiconductor element or the like, and separately acting an electrical connecting function and a physical holding function between an electronic component and a printed wiring substrate.
2. Description of the Related Art
In semiconductor elements as a center of a semiconductor device, it is demanded to satisfy the following requirements with respect to a gate array element mainly used in a microprocessor unit (MPU) or a semiconductor element for OEM use (so-called custom IC). That is, there are demanded requirements of (1) reducing lead inductance for the control of switching noise; (2) efficiently dissipating heat generated due to the increase of power consumed with high speed operation; (3) fining an inner lead in accordance with the increase of input and output terminal number and the fineness of electrodes on the semiconductor element; (4) mounting multi-chips on a single printed wiring substrate for the enlargement of applicable functions; and so on.
In order to satisfy the above requirements, there are proposed various means having the following merits, i.e., (1) the lead inductance may be reduced by rendering the substrate into multi-layer structure; (2) the heat dissipation is surely improved by mounting a heat sink onto a rigid substrate; (3) the inner lead may be fined by utilizing a workability of the substrate; (4) the multi-chips may be mounted on the single substrate by increasing the degree of freedom in the design of the substrate; and so on. These means can effectively be applied to electronic component carriers each formed, for example, by joining the substrate with the lead frame.
A first embodiment of the conventional semiconductor device as shown in Japanese Patent laid open No. 59-98545 is shown in FIG. 1. In this case, a given conductor pattern 2 is formed on an upper surface of a substrate 1 composed of a glass epoxy material and connected to a semiconductor element 3 mounted on a proper place of the substrate 1 with gold wires 4. Furthermore, the conductor pattern 2 is joined to a lead frame 5 for the connection to a given external element through soldering 6. Such an assembly is packaged with a mold resin 7 as a whole.
A second embodiment of the conventional semiconductor device as shown in Japanese Patent laid open No. 59-98545 is shown in FIG. 2. In this case, a given conductor pattern 2 is formed on an upper surface of a substrate 1 composed of a glass epoxy material and connected to a semiconductor element 3 arranged on a proper position of the substrate 1 through an adhesive 8 with gold wires 4. Furthermore, the conductor pattern 2 is joined to a lead frame 5 for the connection to a given external element through soldering 6, while a through-hole 9 is formed in the substrate 1 at a position joined to the lead frame 5. Moreover, such an assembly is locally packaged with a potting resin 7a around the semiconductor element 3.
In the above conventional technique, however, there are the following problems.
[1] Both of electrical connecting function and physical holding function are generally included in the joint portion between the lead frame and the substrate. In the aforementioned conventional technique, it is expected to secure both of electrical connecting function and physical holding function in a joint portion of a main part only by soldering. Now, when such a joint portion is reviewed with respect to the lead frame for mounting high-performance semiconductor element, it is usually related to QFP (Quad Flat Package) capable of having input and output multi-terminals. In such a QFP structure, the joint portion is formed in the outer periphery of four sides, but means for releasing stress based on the difference in thermal expansion between the lead frame and the substrate is not formed, so that such a stress is stored in the joint portion. As a result, when conducting, for example, a life test of a final product, breakage is caused in the joint portion and hence breakage is caused in respective wiring portion.
[2] When the base material is joined to the lead frame through soldering, the joint portion is heated, but when the joint portion and the neighborhood thereof are returned to room temperature after the soldering, stress remains in the joint portion to cause undesirable situations such as warp, distortion and the like. In a step of mounting a semiconductor element, therefore, it is difficult or impossible to conduct the carrying and mounting operations of the semiconductor element due to the occurrence of warp and distortion, and consequently many inferior products are obtained.
[3] In the joining between the lead frame and the substrate, it is necessary to conduct the positioning therebetween with a high accuracy in addition to given heating and pressurizing operations. In fact, the proper positioning is difficult to lower the yield in the joining.
Furthermore, the lead frame 5 is formed by subjecting a lead frame material having a thickness of about 0.15 mm such as 42 alloy, Cu alloy or the like to an etching treatment, so that the pitch between inner leads for the electrical connection to the semiconductor element is usually about 0.20-0.30 mm. If the inner lead is forcedly fined for providing a smaller pitch, there is caused a fear that the strength of the inner lead itself lowers or undesirable crook is generated in the inner lead. In the latter case, the inner lead may be peeled off from the substrate due to stress applied at production steps after the joining.
The conventional semiconductor device is manufactured by a method as disclosed, for example, in Japanese Patent laid open No. 3-203357. That is, a lead provided at its top with a hole having a high lead content solder ball dished thereon is positioned to a through-hole formed in a printed wiring substrate and then the solder ball is reflowed to fill the hole and through-hole with the solder, whereby a soldered joint is formed between the lead and the through-hole.
In the conventional method, however, the lead is merely positioned to the substrate and is not fixed thereto. As a result, when the solder is returned from the heated state to room temperature, thermal stress is directly applied to the soldered joint between the lead and the through-hole, so that there is caused a fear of lowering the reliability in the soldered joint.
Furthermore, it is required to take a long working time for dishing the solder ball on the lead and also the material cost and the like becomes expensive. In addition, a reflowing step for fusing the solder ball is required after the lead dished with the solder ball is positioned to the substrate, which also takes a long working time. Therefore, the working time as a whole becomes long and a finally obtained electronic device becomes more expensive.
Moreover, when using a lead frame for high density packaging having a small pitch between leads and a narrow lead width, it is difficult to dish a solder ball on the hole formed at the top of the lead in an amount of solder required for filling the through-hole and maintaining the reliability of the soldered joint.